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1. 面向 ISE 軟件用戶(hù)的 Vivado Design Suite 高級(jí) XDC 和
   ? 面向 ISE 軟件用戶(hù)的 Vivado Design Suite 高級(jí) XDC 和靜態(tài)時(shí)序分析培訓(xùn)
   Vivado Advanced XDC and Static Timing Analysis for ISE Software Users
   Who Should Attend?
   Existing Xilinx ISE Design Suite FPGA designers
2. Course Outline
   ? 1
   Design Methodology Summary
   Vivado IDE Review
   Accessing the Design Database
   Lab 1:?Vivado IDE Database
   Static Timing Analysis and Clocks
   Lab 2:?Vivado IDE Clocks
   Inputs and Outputs
   Lab 3:I/O Constraints
   Timing Exceptions
   Lab 4:?Timing Exceptions
   ? 2
   Advanced Timing Analysis
   Advanced I/O Interface Constraints
   Lab 5:?Advanced I/O Timing
   Project-Based and Non-Project Batch Design Flows
   Scripting Using Project-Based and Non-Project Batch Flows
   Lab 6a:?Scripting in the Project-Based Flow
   Lab 6b:?Scripting in the Non-Project Batch Flow
   ? 3
   FPGA Design Methodology Checklist
   FPGA Design Methodology
   HDL Coding Techniques
   Reset Methodology
   Lab 5:?Resets
   Lab 6:?SRL and DSP Inference
   Synchronization Circuits and the Clock Interaction Report
   Timing Closure
   FPGA Design Methodology Case Study
   Lab 7:?Timing Closure and Design Conversion
   Appendix: Timing Constraints Review
   Appendix: Synchronization Circuits and the Clock Interaction Report
   Appendix: Fanout and Logic Replication
   Appendix: Pipelining lab
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